The arbitration hardware to access a memory bank external to the line

Each core may access to a BRAM bank external to its line.
The requesting core writes its request in its core_to_line table (64 entries) at the entry matching the target bank in the target line.
In the core_to_line table, the 8 entries associated to the current line are unused (in blue on the figure).
For each core and each target bank, the highest priority request is selected (each core may accumulate multiple requests until each is served by the arbiter).
On the figure, the highest priority entry in each column of each core_to_line table is choosen.
For each target bank, among all the highest priority requests from all the lines, the highest priority line is served (lt on the figure).
On the figure, for a set of eight columns of the same rank in the eight core_to_line tables, the highest priority of these columns is selected.
The arbiter is able to route one request per bank per line per cycle (up to 64 accesses per cycle).
The loaded value is routed from its bank to the line_to_core table entry targetting the requesting core in its line.
From the line_to_core table, the loaded value moves to the from_ram table and then to the core MEMB buffer where it waits for its writeback.