The arbitration hardware to access a memory bank of the line

The 64 cores in LBP are clustered into 8 lines of 8 cores each.
A first level of arbitration gives access from any core in a line to any bank in the same line.
This access uses port B.
The requiring core writes its request into its local to_ram table in the entry matching the BRAM block to access.
As a core has a private access to its own bank, it does not use its own to_ram entry for a line arbitration (light blue squares match unused to_ram entries).
These spare entries are used by the second level arbiter to route its own requests to the banks in the line.
At each cycle, the arbiter selects one access per bank in the line.
The priority changes every cycle to avoid livelocks.
In case of a load, the loaded value is directed to the from_ram table entry matching the requesting core.
In case of a store, the store done signal is written to the from_ram table entry matching the requesting core.
The loaded value is copied from the from_ram table entry to the MEMB buffer to wait for its writeback.